Title :
Pattern Encodability Enhancements for Test Stimulus Decompressors
Author :
Alawadhi, Nader ; Sinanoglu, Ozgur ; Al-Mulla, Mohammed
Author_Institution :
Comput. Sci. Dept., Kuwait Univ., Safat, Kuwait
Abstract :
While scan-based compression is widely utilized in order to alleviate the test time and data volume problems, the overall compression level is dictated not only by the chain to channel ratio but also the ratio of encodable patterns. Aggressively increasing the number of scan chains in an effort to raise the compression levels may reduce the ratio of encodable patterns, degrading the overall compression level. In this paper, we present various methods to improve the ratio of encodable patterns. These methods are based on manipulating the care bit distribution of an unencodable pattern, thereby rendering it compliant with the correlation induced by the decompressor, and thus converting it into an encodable pattern. The proposed methods target improvements over fan-out and XOR decompressors, while they can be utilized to enhance other types of decompressors, such as multiplexer-based ones. Care bit manipulation is effected in the form of selective chain delay, selective slice rotate/invert, or both. By developing computationally efficient algorithms and cost-effective hardware blocks for these manipulation methods, we show that the encodability, and thus the compression levels, of stimulus decompressors can be significantly improved through the proposed practical and design flow compatible solution.
Keywords :
VLSI; circuit testing; logic circuits; care bit manipulation; pattern encodability enhancements; scan chains; test stimulus decompressors; Computer architecture; Computers; Delay; Equations; Hardware; Heuristic algorithms; Logic gates; Pattern encodability; Scan-based test; Test stimulus compression; VLSI test;
Conference_Titel :
Test Symposium (ATS), 2010 19th IEEE Asian
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-8841-4
DOI :
10.1109/ATS.2010.39