Title :
A low power 12-bit and 30-MS/s pipeline analog to digital converter in 0.35μm CMOS
Author :
Rarbi, F. ; Dzahini, D.
Author_Institution :
LPSC Lab., PSI Electron. Co., Grenoble
Abstract :
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash. A CMOS 0.35 mum process is used, and the dynamic range covered is 2 V. The analog part of the converter can be quickly (a couple of mus) switched to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The size of the converterpsilas layout including the digital correction stage is only 1.7 mm*0.6 mm, and the total dc power dissipation is 35 mW.
Keywords :
CMOS integrated circuits; analogue-digital conversion; linear colliders; low-power electronics; pipeline arithmetic; readout electronics; CMOS process; DC power dissipation; ILC ECAL; International Linear Collider; analog to digital converter; converter layout; digital correction; frequency 30 MHz; integrated electronics readout; low power dissipation; pipelined architecture; size 0.35 mum; voltage 2 V; word length 12 bit; Analog-digital conversion; CMOS analog integrated circuits; CMOS process; Coupling circuits; Dynamic range; Pipelines; Power dissipation; Preamplifiers; Switching circuits; Switching converters; Analog-digital conversion; CMOS analog integrated circuits; Pipelined converter; Switched-capacitors;
Conference_Titel :
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-1810-7
Electronic_ISBN :
978-1-4244-1811-4
DOI :
10.1109/ICICDT.2008.4567263
