Sleep circuit for SRAM core with improved noise-margin

Data retention power gating is a commonly used method for leakage reduction in deep submicron SRAM. However, application of such methods result into reduced stability of the SRAM bitcell. Moreover, reducing supply voltage and increasing process variation put a limitation on such usage in deep submicron processes. Present scheme describes a method to enhance stability while applying such data retention power gating to SRAM memory core. Method improves stability under cross-corner/high-leakage conditions using a feedback mechanism. Minimum functional voltage under data retention power gating is reduced up to 11% of VDD using the described scheme, while using 90 nm CMOS process. The scheme enables the memory usage under low voltage operation, where we observe data retention failures using normal gating methods.