Low power clocking strategies in deep submicron technologies

Author

Hosny, M. Samy ; Wu, Yuejian

Author_Institution

SiliconPro, Ottawa, ON

fYear

2008

fDate

2-4 June 2008

Firstpage

143

Lastpage

146

Abstract

Recent silicon process technology advancements have given chip designers integration capabilities never were possible before, and have led to a new wave of complex ASICs (applied specific integrated circuits). These advanced processes come with new challenges. This paper presents some of the challenges in deep submicron technologies, which require new design practices. We demonstrate some issues related to clocking strategies and timing closure that were encountered during the design of a FEC40 ASIC, and a methodology is proposed to mitigate some of these issues. The FEC40 ASIC is a forward error correction chip designed for Nortelpsilas 40 Gb/s coherent optical transmission system. The chip has about 11 million gates at a core frequency of 350 MHz and has 70 clock domains. The chip was fabricated in a 90 nm technology.

Keywords

application specific integrated circuits; forward error correction; integrated circuit design; low-power electronics; FEC40 ASIC; Si; applied specific integrated circuits; bit rate 40 Gbit/s; deep submicron technologies; forward error correction chip; frequency 350 MHz; low power clocking strategies; silicon process technology; size 90 nm; Application specific integrated circuits; Clocks; Delay effects; Integrated circuit interconnections; Integrated circuit technology; Manufacturing processes; Process design; Temperature; Timing; Voltage; Clock Gating; On Chip Variation (OCV); Static Timing Analysis; deep submicron technologies;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567265

Filename

4567265