Overview of DFT features of the Sun Microsystems Niagara2 CMP/CMT SPARC chip

Author

Ziaja, Tom ; Gala, Murali

Author_Institution

Sun Microsyst., Inc., Santa Clara, CA

fYear

2008

fDate

2-4 June 2008

Firstpage

151

Lastpage

154

Abstract

The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed defects. In addition, this paper addresses issues involved in SOC testing in the absence of IEEE 1500.

Keywords

built-in self test; design for testability; logic circuits; system-on-chip; CMP; CMT SPARC chip; DFT features; SOC testing; design-for-test features; memory built-in-self-test; scan-based testing; sun microsystems Niagara2; system-on-chip; Automatic test pattern generation; Built-in self-test; Design for testability; Ethernet networks; Libraries; Logic arrays; Logic design; Logic testing; Manufacturing; Sun; CMT; Logic BIST; SOC; memory test; microprocessor test; transition test;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567267

Filename

4567267