Title :
Chip Level Reliability of MANOS Cells under Operating Conditions
Author :
Choi, Eun-Seok ; Kim, Se-Jun ; Seo, Soon-Ok ; Yoo, Hyun-Seung ; Park, Kyoung-Hwan ; Jung, Sung-Wook ; Lim, Se-Yun ; Joo, Han-Soo ; Kim, Gyo-Ji ; Lee, Sang-Bum ; Oh, Sang-Hyun ; Om, Jae-Chul ; Yi, Jeong-Hyong ; Lee, Seok-Kiu
Author_Institution :
Memory R&D, Hynix Semicond. Inc., Icheon
Abstract :
MT reliability of MANOS cell was examined from cell array. Lots of retention tail bits occurred even at RT. The fail cells were classified as the manner of q-loss. Defective cell lost abundant charge at early stage, while the q-loss rate of worse cell was faster and lasted in a certain period. Si-cluster in our nitride was supposed to make the worse cell, and this cell redeemed its retention capability by reducing shallow trap in Si-rich nitride.
Keywords :
flash memories; integrated circuit design; integrated circuit reliability; integrated memory circuits; silicon compounds; MANOS cell; MT reliability; SiN; chip level reliability; defective cell; q-loss rate; silicon cluster; silicon rich nitride; temperature 293 K to 298 K; Bonding; Curing; Kinetic energy; Nonvolatile memory; Probability distribution; Research and development; Scalability; Semiconductor device reliability; Tail; Temperature;
Conference_Titel :
Memory Workshop, 2009. IMW '09. IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4244-3762-7
DOI :
10.1109/IMW.2009.5090584
