• DocumentCode
    2169614
  • Title

    Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell

  • Author

    Khellah, Muhammad M. ; Keshavarzi, Ali ; Somasekhar, Dinesh ; Karnik, Tanay ; De, Vivek

  • Author_Institution
    Circuits Res. Lab., Intel Corp, Hillsboro, OR
  • fYear
    2008
  • fDate
    2-4 June 2008
  • Firstpage
    185
  • Lastpage
    188
  • Abstract
    We review circuit techniques aimed at improving read and write stability of the smallest 6T SRAM cell typically used in microprocessorpsilas Last Level cache (LLC). We qualitatively compare three main approaches and give a designerpsilas perspective on the pros and cons of the different schemes.
  • Keywords
    SRAM chips; cache storage; circuit stability; dense 6T SRAM cell; last level cache; microprocessor; read and write circuit; read and write stability; Circuits; Decision support systems; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4244-1810-7
  • Electronic_ISBN
    978-1-4244-1811-4
  • Type

    conf

  • DOI
    10.1109/ICICDT.2008.4567275
  • Filename
    4567275
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2169614