Interconnect and cell redundancy tradeoffs for WSI: an FFT case study

The authors describe the results of an investigation into the relationship between cell redundancy, yield, and interconnect area for WSI (wafer scale integration) designs. A general analysis framework is presented which allows algorithmic computation of the optimum amount of redundancy from an area efficiency standpoint. The results of this theoretical study were applied to the case study of an 8-point FFT (fast Fourier transform) WSI design which uses a novel architecture requiring only two functional cell types. The optimum design point and predicted cell yield are identified for this case study