Title :
A Method of Phase-Locked Loop Performance Testing
Author :
Zhang, Ping ; Zhang, Jianmin ; Song, Yanmin ; Deng, Qinxue ; Xing, Zuocheng
Author_Institution :
Sch. of Electron. Eng., Tianjin Univ. of Technol. & Educ., Tianjin, China
Abstract :
In general, CPU may upgrade its frequency by the PLL (phase-locked loop), but the cost of testing is very expensive for high frequency signals. This paper introduces the method that inserts test logics in the CPU to implement its PLL performance testing. It is very easy to implement, and reduces effectively test costs in the case of low hardware overheads. The result shows that the test logics can fulfill the PLL performance testing.
Keywords :
integrated circuit testing; logic testing; microprocessor chips; phase locked loops; CPU; PLL performance testing; frequency upgrading; hardware overhead; high-frequency signal; phase-locked loop performance testing method; test logics; Central Processing Unit; Circuit stability; Circuit testing; Clocks; Costs; Frequency; Logic circuits; Logic testing; Phase locked loops; Test equipment;
Conference_Titel :
Image and Signal Processing, 2009. CISP '09. 2nd International Congress on
Conference_Location :
Tianjin
Print_ISBN :
978-1-4244-4129-7
Electronic_ISBN :
978-1-4244-4131-0
DOI :
10.1109/CISP.2009.5304624
