• DocumentCode
    2169662
  • Title

    HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC

  • Author

    Mirza-Aghatabar, Mohammad ; Breuer, Melvin A. ; Gupta, Sandeep K.

  • Author_Institution
    Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
  • fYear
    2010
  • fDate
    1-4 Dec. 2010
  • Firstpage
    249
  • Lastpage
    254
  • Abstract
    In this paper we present an efficient heuristic to significantly enhance yield/area of die in technologies where the inherent yield is low. Our technique makes use of a judicious use of redundancy and switching circuitry. Though our presentation is focused on pipeline (linear) structures, our techniques can be extended to apply to more general structures. The time complexity of our procedure is O(n3) for an n-stage pipeline.
  • Keywords
    integrated circuit yield; redundancy; switching circuits; system-on-chip; HYPER; SoC; die; efficient heuristic; n-stage pipeline; pipeline linear structures; redundancy; switching circuitry; time complexity; yield/area improvement; Circuit faults; Complexity theory; Dynamic programming; Integrated circuit reliability; Pipelines; Redundancy; System-on-a-chip; SoC; heuristic; redundancy; yield/area;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium (ATS), 2010 19th IEEE Asian
  • Conference_Location
    Shanghai
  • ISSN
    1081-7735
  • Print_ISBN
    978-1-4244-8841-4
  • Type

    conf

  • DOI
    10.1109/ATS.2010.51
  • Filename
    5692255
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2169662