FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications

Author

PUGET, Sophie ; BOSSU, Germain ; Fenouiller-Beranger, C. ; Perreau, Pierre ; Masson, Pascal ; Mazoyer, Pascale ; Lorenzini, Philippe ; Portal, Jean-Michel ; BOUCHAKOUR, Rachid ; Skotnicki, Thomas

Author_Institution

STMicroelectronics, Crolles

fYear

2009

fDate

10-14 May 2009

Firstpage

1

Lastpage

2

Abstract

A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time. A similar value of 10 ms at 85degC is obtained like for impact ionization (II) optimised devices.

Keywords

DRAM chips; low-power electronics; silicon-on-insulator; FDSOI floating body cell eDRAM; GIDL mechanism; capacitorless 1T-DRAM cell; gate-induced drain-leakage; low power application; size 19 nm; size 20 nm; size 9.5 nm; write operation; Diodes; Energy consumption; Impact ionization; Semiconductor films; Silicon; Steady-state; Substrates; Transistors; Tunneling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop, 2009. IMW '09. IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4244-3762-7

Type

conf

DOI

10.1109/IMW.2009.5090590

Filename

5090590