DocumentCode :
2169775
Title :
Wafer level burn-in
Author :
Conti, Dennis R. ; Van Horn, Jody
Author_Institution :
Gen. Technol. Div., IBM Corp., Essex Junction, VT, USA
fYear :
2000
fDate :
2000
Firstpage :
815
Lastpage :
821
Abstract :
Is it the industry´s intent to apply wafer-level burn-in (WLBI) to MPUs and ASICs? Package-level burn-in (PLBI) today is facing escalating burn-in power dissipation for these MPU and ASIC devices. The burn-in board (BIB) density (devices/BIB) varies inversely with device power dissipation. However, wafer-level burn-in would indicate the opposite-more devices in a 200 mm diameter. Is it the industry´s intent to apply wafer-level burn-in to memory and more specifically, to DRAM? Here, the power situation is much less problematic than MPUs and ASICs. Yet, unlike logic DRAMs are overwhelmingly wirebonded die which require a test interface (probe) that can penetrate the bond pad´s aluminum oxide without damaging the wafer. There are multi-device under test (DUT) probe technologies available today for ×32 DUT testing; they can cover an area of four square inches. And it may be possible to leverage these technologies to provide full wafer contact-but not for free. How would these compare to the PLBI economic model that we know and love? In the 1993-94 timeframe, several technology issues concerning WLBI were considered risky and required years to solve. So where is the design point today? Is WLBI a static burn-in methodology where applying elevated voltage and temperature is sufficient? Is it dynamic burn-in? Monitored burn-in? In situ burn-in? Or, will it naturally progress to wafer-level test and burn-in (WLTB)? This paper provides an overview of wafer-level burn-in, past and present, and offers a prediction for the future
Keywords :
integrated circuit testing; ASIC; DRAM; DUT testing; MPU; burn-in board density; package-level burn-in; power dissipation; wafer-level burn-in; Aluminum oxide; Application specific integrated circuits; Logic devices; Logic testing; Packaging; Power dissipation; Probes; Random access memory; Wafer bonding; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-5908-9
Type :
conf
DOI :
10.1109/ECTC.2000.853255
Filename :
853255
Link To Document :
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