Title :
Performance criteria for evaluating the importance of on-chip inductance
Author :
Ismail, Yehea I. ; Friedman, Eby G. ; Neves, Jose L.
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
fDate :
31 May-3 Jun 1998
Abstract :
Two figures of merit are presented for determining whether a section of interconnect should be modeled as either an RLC or an RC impedance. The attenuation that a signal undergoes as it propagates a distance equal to the length of the interconnect line is shown to be a useful figure of merit. The second figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. Circuit simulations of an RLC transmission line and a five section RC II circuit are used to quantify and determine the relative accuracy of an RC model. One primary result of this study is evidence demonstrating that a range of interconnect length exists for which inductance effects are prominent. It is also shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect
Keywords :
VLSI; circuit analysis computing; digital simulation; inductance; integrated circuit interconnections; integrated circuit modelling; RC impedance; RLC impedance; attenuation; figure of merit; inductance effects; interconnect length; interconnect section; on-chip inductance; performance criteria; rise time; Attenuation; Delay; Distributed parameter circuits; Impedance; Inductance; Integrated circuit interconnections; Power transmission lines; RLC circuits; Superconducting transmission lines; Wires;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706887