Title :
A 4-channel analog front end for 25.6 Mbps ATM switches
Author :
Loh, K. Lawrence ; Narayan, Sriram ; Kuo, Augustine ; Mohapatra, Subrat
Author_Institution :
Cirrus Logic Inc., Fremont, CA, USA
Abstract :
This chip integrates four 32 MHz channels for twisted-pair cable digital communication using a 0.5 um digital CMOS process. The implementation features all major analog signal processing blocks on chip with a minimum number of offchip passive components. A PLL is used to provide transmit clocks as well as to center four pairs of gated VCOs for data synchronization. A 1st-order adaptive equalizer is designed to provide proper high-frequency boosting for different lengths of connecting cables. A current-mode filter with direct current amplification is used to provide output pulse shaping to conform 25.6 Mbps ATM output waveform templates. The power dissipation is measured at 1.3 W (325 mW per channel) during full operation of all 4 channels
Keywords :
CMOS analogue integrated circuits; adaptive equalisers; analogue processing circuits; asynchronous transfer mode; digital communication; electronic switching systems; mixed analogue-digital integrated circuits; phase locked loops; pulse shaping circuits; synchronisation; twisted pair cables; voltage-controlled oscillators; 0.5 micron; 1.3 W; 1st-order adaptive equalizer; 25.6 Mbit/s; 4-channel analog front end; ATM switches; PLL; analog signal processing blocks; current-mode filter; data synchronization; digital CMOS process; direct current amplification; gated VCOs; high-frequency boosting; output pulse shaping; transmit clocks; twisted-pair cable digital communication; Adaptive signal processing; Asynchronous transfer mode; CMOS process; Clocks; Communication cables; Communication switching; Digital communication; Phase locked loops; Switches; Synchronization;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606636
