Title :
15 nm gate length planar CMOS transistor
Author :
Bin Yu ; Haihong Wang ; Joshi, A. ; Qi Xiang ; Effiong Ibok ; Ming-Ren Lin
Author_Institution :
Strategic Technol. Group, Adv. Micro Devices, Sunnyvale, CA, USA
Abstract :
Continued scaling of mainstream planar CMOS transistor technology into the deep-sub-100 nm regime is increasingly challenging but possible. In this paper, we report bulk-silicon planar CMOS transistors with the physical gate length scaled down to 15 nm. Gate delays (CV/I) of 0.29 ps for n-channel FET and 0.68 ps for p-channel FET are achieved at a supply voltage of 0.8 V. Energy-delay products are 42 pJ-ps/m for an n-channel FET and 97 pJ-ps/m for a p-channel FET, respectively. To our knowledge; these numbers are the best reported to date.
Keywords :
CMOS integrated circuits; MOSFET; VLSI; elemental semiconductors; nanotechnology; silicon; 0.29 ps; 0.68 ps; 0.8 V; 15 nm; Si; bulk-Si CMOSFETs; channel profile design; gate delays; gate dielectrics scaling; high-k gate dielectric; n-channel FET; p-channel FET; physical gate length scaling; planar CMOS transistor technology; ultra-shallow junction; CMOS technology; Delay; Dielectrics; FETs; Fabrication; Lithography; Oxidation; Scalability; Transistors; Voltage;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979669
