On-chip circuit for measuring jitter and skew with picosecond resolution

Author

Jenkins, K.A. ; Jose, A.P. ; Xu, Z. ; Shepard, K.L.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY

fYear

2008

fDate

2-4 June 2008

Firstpage

257

Lastpage

260

Abstract

A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network to obtain on-chip period jitter and clock skew measurements.

Keywords

clocks; integrated circuit measurement; integrated circuit testing; jitter; logic testing; clock distribution network; clock skew measurements; frequency 2 GHz; jitter resolution; long-term jitter; on-chip circuit; on-chip period jitter measurements; picosecond resolution; voltage-controlled delay element; Circuits; Clocks; Delay effects; Latches; Oscilloscopes; Phase measurement; Semiconductor device measurement; Time measurement; Timing jitter; Voltage; Jitter; built-in self test; clock distribution; clock skew; long-term jitter; on-chip measurement; period jitter; tracking jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567290

Filename

4567290