Interconnect inductance effects on delay and crosstalk for long on-chip nets with fast input slew rates

In this paper, we address the significance of parasitic inductance on designing signal coupling shields and clock tree distributions in terms of input slew rate and interconnect length by using 3D RLC parasitic extraction and Spice simulation for 500 MHz clocks and 0.15 μm process interconnect technology. We report a larger crosstalk deviation under fast input slew rates and a higher clock skew variation due to wiring inductive effect for low resistive long nets which should be considered for future high-speed design. In addition, we propose a feasible one-level interleaved clock shielding scheme with optimized dimensions for a minimal clock skew and compare it to a worst case signal coupling three-level clock shielding scheme