Author :
Gay, G. ; Molas, G. ; Bocquet, M. ; Jalaguier, E. ; Gély, M. ; Masarotto, L. ; Colonna, J.P. ; Grampeix, H. ; Martin, F. ; Brianceau, P. ; Vidal, V. ; Kies, R. ; Yckache, K. ; De Salvo, B. ; Ghibaudo, G. ; Baron, T. ; Bongiorno, C. ; Lombardo, S.
Abstract :
In this work, memory devices integrating a double layer of silicon nanocrystals as trapping medium and a high-k HfAlO-based control dielectric are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared to the single Si-nc layer devices, without introducing dispersions on the charging dynamics. Then, we also evaluate the potentiality of hybrid Si-nc double layer/SiN layer charge trapping media. These devices show a good memory window and good retention (>3 V after 10 years) with small activation energy (0.35 eV up to 200degC), thus being promising for future high-temperature memory applications.
Keywords :
elemental semiconductors; flash memories; hafnium compounds; high-k dielectric thin films; high-temperature electronics; nanoelectronics; nanostructured materials; semiconductor device reliability; silicon; silicon compounds; wide band gap semiconductors; HfAlO-Si; Si-SiN; activation energy; charge trapping medium; charging dynamics; double layer memory device reliability; flash memory; high-k control dielectrics; high-temperature memory; memory window; Dielectric devices; Fabrication; High K dielectric materials; High-K gate dielectrics; Nanocrystals; Nonvolatile memory; Robustness; Silicon compounds; Temperature; Tin;
