A transmitter and receiver interface circuit including an equalizer and PFLL for 150 Mbit/s cable communication

Author

Routama, J. ; Koli, K. ; Ruhanen, P. ; Halonen, K.

Author_Institution

Lab. of Electron. Circuit Design, Helsinki Univ. of Technol., Espoo, Finland

fYear

1997

fDate

5-8 May 1997

Firstpage

315

Lastpage

318

Abstract

This paper describes a single chip transmitter and receiver interface circuit for 150 Mbit/s CMI-coded data transmission. The receiver circuit includes a 12 dB cable equalizer to compensate nonconstant cable attenuations and a PFLL for data regeneration. The transmitter includes a cable driver which supplies a stable IVpp signal amplitude to the transmission line and a PLL to extract a 310 MHz clock signal

Keywords

data communication; equalisers; phase locked loops; receivers; telecommunication cables; transmitters; 150 Mbit/s; CMI-coded data transmission; PFLL; attenuation compensation; cable communication; data regeneration; driver; equalizer; interface circuit; receiver; single chip; transmission line; transmitter; Attenuation; Communication cables; Data communication; Data mining; Distributed parameter circuits; Driver circuits; Equalizers; Phase locked loops; Power cables; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606637

Filename

606637

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2170081