DocumentCode
2170130
Title
Power efficient rapid system prototyping using CoDel: the 2D DWT using lifting
Author
Agarwal, Nainesh ; Dimopoulos, Nikitas
Author_Institution
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
fYear
2005
fDate
24-26 Aug. 2005
Firstpage
550
Lastpage
553
Abstract
In this report, we present CoDel, a rapid hardware prototyping language, to implement a DSP module which performs the biorthogonal two-dimensional discrete wavelet transform using the lifting technique. Specifically, we implement the wavelet transform using the Le Gall integer-to-integer 5/3 filter bank. Using CoDel, we show how this wavelet transform can be implemented with just a few lines of code. We show how CoDel facilitates clock gating reducing dynamic power dissipation. We develop and use a state level power analysis framework, and determine that power savings of 16% can be expected.
Keywords
channel bank filters; digital signal processing chips; discrete wavelet transforms; specification languages; 2D DWT; DSP module; biorthogonal 2D discrete wavelet transform; clock gating; dynamic power dissipation; integer-to-integer filter bank; lifting technique; power efficient rapid system prototyping; rapid hardware prototyping language; state level power analysis framework; Discrete wavelet transforms; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers and signal Processing, 2005. PACRIM. 2005 IEEE Pacific Rim Conference on
Print_ISBN
0-7803-9195-0
Type
conf
DOI
10.1109/PACRIM.2005.1517348
Filename
1517348
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