Title :
Scalability of Fully Planar NAND Flash Memory Arrays Below 45nm
Author :
Blomme, Pieter ; Van Houdt, Jan
Author_Institution :
IMEC, Heverlee
Abstract :
We have simulated the coupling ratios in fully planar NAND arrays. We have shown that floating gate interference is no fundamental limitation for channel lengths down to 15 nm. The main limitation for scaling NAND arrays is the loss of control gate coupling due to fringing fields, leading to a strong increase in the programming voltage of the memory cells, even when using a 5 nm EOT IPD.
Keywords :
NAND circuits; flash memories; NAND flash memory arrays; capacitance simulations; control gate; floating gate; interpoly dielectric; size 40 nm; Character generation; Dielectric losses; High K dielectric materials; High-K gate dielectrics; Interference; Nonvolatile memory; Parasitic capacitance; Scalability; Thickness control; Voltage control;
Conference_Titel :
Memory Workshop, 2009. IMW '09. IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4244-3762-7
DOI :
10.1109/IMW.2009.5090607
