Facing pipeline false dependencies using VRB table

The number of physical registers is one of the critical issues of current superscalar out-of-order processors. A system and method for register renaming which allocates physical registers when instructions complete execution is renaming with virtual registers. In this way register pressure is significantly reduced. This method needs two map tables (GMT and PMT) which may be delayed due to the necessity of looking them up. The proposed renaming scheme in this paper provides the advantages of banking the virtual and physical registers and adding two pointers to eliminate the need of any map table as well as free lists for physical and virtual registers.