Linearized sub-optimum method of long wire interconnections with uniform wire driver

A simple analysis is made of the delay for a uniform long wire interconnection with distributed RC property. The optimal widths of wire and transistor are investigated under different constraints. The analysis is based on an improved switch model and Elmore delay model. A linearized relation between wire width and transistor width is suggested. Performance comparison is made between the absolute optimum and the suggested method by plotting the loci of the optimum solutions. Results show that the linearized relation can achieve a sub-optimum solution quite close to the absolute optimum, and it can be used in the delay calculation