Statistical leakage modeling in CMOS logic gates considering process variations

The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical process variations. The developed methodology is completely based on BSIM4 equations, implemented in Verilog-A, and applicable to any different CMOS technologies (90 nm, 65 nm, etc), electrical simulators and models. For the first time subthreshold, gate, BTBT, and GIDL leakage variations are considered. Comparisons to Monte-Carlo simulation on 90 and 65 nm STMicroelectronics CMOS technologies fully validate the accuracy of the proposed method and demonstrate the efficiency of the proposed analysis method.