Title :
Robust delay-fault test generation and synthesis for testability under a standard scan design methodology
Author :
Cheng, Kwang-Ting ; Devadas, Srinivas ; Keutzer, Kurt
Author_Institution :
AT&T Bell Laboratories
Keywords :
Circuit faults; Circuit synthesis; Circuit testing; Delay; Design methodology; Logic testing; Robustness; Sequential analysis; Sequential circuits; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
