DocumentCode
2170417
Title
Intelligent simulation-based lot scheduling of photolithography toolsets in a wafer fabrication facility
Author
Arisha, Amr ; Young, Paul
Author_Institution
Sch. of Mech. & Manuf. Eng., Dublin City Univ., Ireland
Volume
2
fYear
2004
fDate
5-8 Dec. 2004
Firstpage
1935
Abstract
Scheduling of a semiconductor manufacturing facility is one of the most complex tasks encountered. Confronted with a high technology product market, semiconductor manufacturing is increasingly more dynamic and competitive in the introduction of new products in shorter time intervals. Photolithography, being one of the processes repeated often, is a fabrication bottleneck. Lot scheduling within photolithography is a challenging activity where substantial improvements in factory performance can be made. The proposed scheduling methodology integrates two common approaches, simulation and artificial intelligence. Using detailed simulation modeling within a structured modeling method, a comprehensive model to characterize the photolithography process was developed. An artificial intelligence scheduler was then developed and integrated with the model with the goal of reducing work-in-process (WIP), setup time, and throughput time. The results have shown a significant improvement in lot cycle time as well as tool utilization, improved the throughput time by an average of 15% and is currently in use for scheduling the photolithography process.
Keywords
digital simulation; electronic engineering computing; integrated circuit manufacture; intelligent manufacturing systems; photolithography; production engineering computing; scheduling; artificial intelligence; high technology product market; intelligent simulation-based lot scheduling; photolithography toolsets; semiconductor manufacturing facility; simulation modeling; structured modeling method; wafer fabrication facility; work-in-process; Artificial intelligence; Fabrication; Job shop scheduling; Lithography; Manufacturing processes; Production facilities; Semiconductor device manufacture; Semiconductor device modeling; Throughput; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation Conference, 2004. Proceedings of the 2004 Winter
Print_ISBN
0-7803-8786-4
Type
conf
DOI
10.1109/WSC.2004.1371552
Filename
1371552
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