DocumentCode :
2170458
Title :
Over-coated flip-chip fine package development for MCM fabricated with Si IC and GaAs MMIC
Author :
Kurata, Hiroyuki ; Ogata, Toshihiro ; Mitsuka, Kaoru ; Matsushita, Hikari
Author_Institution :
Semicond. Technol. HQ, New Japan Radio Co., Kamifukuoka City, Japan
fYear :
2000
fDate :
2000
Firstpage :
949
Lastpage :
954
Abstract :
A newly developed over-coated Flip-chip Fine Package (ocFFP) and its assembly line are presented in this paper. OcFFP is a kind of chip scale package (CSP) and has several novel features that are small in size, light in weight, high reliability, MCM-suitability and applicability to high-speed chip mounter. They are suitable for portable communication equipments, requiring smaller, lighter and lower cost IC packages. Developed ocFFP is 0.5 mm pin pitch, 24 pin counts and 3.5×3.5×0.85 mm package size in which 1.04×1.42×0.2 mm Si IC and 1.37×1.38×0.2 mm GaAs MMIC are flip chip bonded. Al2O3 arrayed substrate is used and, its size is 59×91×0.35 mm containing with 196 pieces of 3.5×3.5 mm package size. Assembly processes of the ocFFP are as follows. The flip chip bonding is accomplished with Au bumps on ICs and Au metal pattern on the ceramic substrate by thermosonic technology. This method reduces bonding temperature and time. This method is key technology to achieving low cost. The narrow gap between the ceramic substrate and the chips is filled with underfill resin, and the array substrate is coated with over-coating resin. The over-coating resin has low flexural modulus results in less substrate warpage by the resin constriction. In underfill and ever-coating processes, a same machine is used changing resin and program. After ink marking, the assembled array substrate is separated into the individual package pieces by dicing. And each ocFFP is picked up, tested and put into emboss-tape continuously. Reliability test and board level reliability test showed no failure
Keywords :
III-V semiconductors; MMIC; chip scale packaging; elemental semiconductors; flip-chip devices; gallium arsenide; integrated circuit packaging; multichip modules; silicon; GaAs; GaAs MMIC; MCM fabrication; Si; Si IC; chip scale package; over-coated flip-chip fine package; Assembly; Bonding; Chip scale packaging; Costs; Flip chip; Gold; Integrated circuit packaging; Packaging machines; Resins; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-5908-9
Type :
conf
DOI :
10.1109/ECTC.2000.853281
Filename :
853281
Link To Document :
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