• DocumentCode
    2170489
  • Title

    Using square array structures in parallel ATPG

  • Author

    Shi, Zhimin ; Gillard, Paul

  • Author_Institution
    Dept. of Comput. Sci., Memorial Univ. of Newfoundland, St. John´´s, Nfld., Canada
  • fYear
    1993
  • fDate
    14-17 Sep 1993
  • Firstpage
    486
  • Abstract
    This paper proposes a novel parallel processing architecture for test pattern generation. Experimental results show that this architecture has the potential ability to produce super-linear speedup for ATPG, for some difficult cases
  • Keywords
    logic testing; parallel architectures; parallel processing; parallel ATPG; parallel processing; square array structures; super-linear speedup; test pattern generation; Automatic test pattern generation; Communication networks; Computer architecture; Computer networks; Joining processes; Parallel processing; Search methods; Telecommunication traffic; Test pattern generators; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 1993. Canadian Conference on
  • Conference_Location
    Vancouver, BC
  • Print_ISBN
    0-7803-2416-1
  • Type

    conf

  • DOI
    10.1109/CCECE.1993.332345
  • Filename
    332345
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2170489