DocumentCode :
2170597
Title :
User-centric design space exploration for heterogeneous Network-on-Chip platforms
Author :
Chou, Chen-Ling ; Marculescu, Radu
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
fYear :
2009
fDate :
20-24 April 2009
Firstpage :
15
Lastpage :
20
Abstract :
In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the network-on-chip (NoC) approach. As a novel contribution, we consider explicitly the information about the user experience into a design flow which aims at minimizing the workload variance; this allows the system to better adapt to different types of user needs and workload variations. More specifically, we first collect various user traces from various applications and generate specific clusters using machine learning techniques. For each cluster of such user traces, depending on the architectural parameters extracted from high-level specifications, we propose an optimization method to generate the NoC system architecture. Finally, we validate the user-centric design space exploration using realistic traces and compare it to the traditional NoC design methodology.
Keywords :
circuit analysis computing; learning (artificial intelligence); logic design; network-on-chip; optimisation; NoC system architecture; heterogeneous network-on-chip platforms; machine learning techniques; optimization method; user-centric design space exploration; Computer architecture; Constraint optimization; Design methodology; Design optimization; Job shop scheduling; Machine learning; Network-on-a-chip; Processor scheduling; Runtime; Space exploration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
ISSN :
1530-1591
Print_ISBN :
978-1-4244-3781-8
Type :
conf
DOI :
10.1109/DATE.2009.5090626
Filename :
5090626
Link To Document :
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