Computational ordering of adaptive digital networks under pipeline constraints and its application to DSP compilers

Author

Sugino, Nobuhiko ; Vilasdechanon, Jirasuk ; Likit-Anurucks, Kiti ; Nishihara, Akinori

Author_Institution

Dept. of Phys. Electron., Tokyo Inst. of Technol., Japan

fYear

1996

fDate

18-21 Nov 1996

Firstpage

101

Lastpage

104

Abstract

A novel computational ordering of adaptive digital networks for a digital signal processor (DSP) with multiple stages of pipeline is proposed. Optimization techniques for conditional branches are also introduced. By use of these methods, the number of overhead codes related to pipeline hazards and delayed branches is reduced

Keywords

adaptive filters; adaptive signal processing; circuit CAD; circuit layout CAD; circuit optimisation; digital filters; digital signal processing chips; hazards and race conditions; pipeline processing; DIMPL compiler; DSP compilers; adaptive digital networks; computational ordering; conditional branches; delayed branches; digital signal processor; filter; multiple pipeline stages; optimization techniques; overhead codes; pipeline constraints; pipeline hazards; Adaptive filters; Adaptive systems; Computer networks; Digital filters; Digital signal processing; Electronic circuits; Finite impulse response filter; Physics computing; Pipeline processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-3702-6

Type

conf

DOI

10.1109/APCAS.1996.569229

Filename

569229