A 42 MB/S multi-channel digital adaptive beamforming QAM demodulator for wireless applications

A VLSI implementation of an integrated complete adaptive beamforming processor and QAM demodulator is presented. The adaptive beamforming processor includes variable number of adaptive beamforming channel combining, a fully writable training processor, a programmable adaptive beamforming control processor, and a microcontroller interface. Interleaving area intensive blocks such as the Nyquist filters and multipliers is often employed to save chip area and thus enable the integration of all these features into a single chip. This chip can operate as a stand alone adaptive beamforming QAM demodulator, or it can work together with an adaptive equalizer for the high bit-rate indoor wireless applications. In a 2.22 dB SINR interference environment, the receiver achieves a link quality of 32.6 dB SNR by the digital adaptive beamforming processing