Integration of multi-level self-aligned CoWP barrier compatible with high performance BEOL

Author

Chhun, S. ; Gosset, L.G. ; Besling, W. ; Vanypre, T. ; Brun, Ph. ; Oilier, E. ; Mellier, M. ; Imbert, G. ; Jullian, S. ; Margain, A. ; Guillan, J. ; Gras, R. ; Dupuy, J.-C. ; Torres, J.

Author_Institution

R&D, Philips Semicond., Crolles

fYear

2006

fDate

5-7 June 2006

Firstpage

33

Lastpage

35

Abstract

A hybrid CoWP/SiCN Cu passivation was integrated in a three-metal-level interconnect stack at 65 nm technology node using a porous ULK material (K=2.5). 5 and 20 nm thick Pd-free CoWP electroless barriers were evaluated using a standard trench first hard mask architecture (TFHM) integration scheme, with PVD, ALD or punch-through Ta-based metallization processes. This study evidenced strong interaction between CoWP and etching chemistries, inducing feature size modification. Results evidenced the successful integration of an ultra-thin electroless barrier with slight process tuning, whereas thicker one still requires specific etch process development or integration scheme modification

Keywords

integrated circuit interconnections; integrated circuit metallisation; low-k dielectric thin films; passivation; vapour deposited coatings; 20 nm; 5 nm; 65 nm; ALD process; BEOL; CoWP; Cu; PVD process; SiCN; TFHM integration; Ta; ULK material; copper passivation; electroless barrier; etching chemistry; feature size modification; punch-through metallization; three-metal-level interconnect; trench first hard mask architecture; Atherosclerosis; Chemical technology; Chemistry; Dielectrics; Electromigration; Etching; Inorganic materials; Leakage current; Metallization; Protection;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2006 International

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-0104-6

Type

conf

DOI

10.1109/IITC.2006.1648638

Filename

1648638