DocumentCode
2170999
Title
Area reduction techniques for BIST PLA´s
Author
Macii, Enrico ; Wolf, Tara
Author_Institution
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
fYear
1993
fDate
14-17 Sep 1993
Firstpage
590
Abstract
Programmable Logic Arrays (PLA´s) are widely used in VLSI systems because of their compactness, ease in automatic design, and regularity in their structure. This paper describer some techniques to reduce the chip area of a PLA containing self-testing circuitry. In particular, we introduce some variants to the method presented which allow us to further minimize the amount of logic required to realize the BIST mechanism. Some experimental results on the implementation of a real self-testing PLA are given in order to show the effectiveness of our approach
Keywords
VLSI; built-in self test; integrated circuit testing; logic arrays; logic design; logic testing; BIST; PLA; VLSI systems; area reduction techniques; chip area; programmable logic arrays; self-testing circuitry; Automatic logic units; Automatic testing; Built-in self-test; Circuit testing; Decoding; Informatics; Logic testing; Programmable logic arrays; Registers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1993. Canadian Conference on
Conference_Location
Vancouver, BC
Print_ISBN
0-7803-2416-1
Type
conf
DOI
10.1109/CCECE.1993.332364
Filename
332364
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