DocumentCode :
2171019
Title :
New etch challenges for the 65-nm technology node Low-k integration using An enhanced Trench First Hard Mask architecture
Author :
Possémé, N. ; Maurice, C. ; Brun, Ph. ; Oilier, E. ; Guillermet, M. ; Vérove, C. ; Berger, T. ; Fox, R. ; Hinsinger, O.
Author_Institution :
CEA-LETI, Crolles
fYear :
2006
fDate :
5-7 June 2006
Firstpage :
36
Lastpage :
38
Abstract :
In this paper, an enhanced trench first hard mask (TFHM) 300mm low-k backend integration is studied for the 65nm technology node. This new integration scheme leads to new etch challenge (selectivity, residues or hard mask faceting). An approach change from full via to partial via has been evaluated. Electrical data have also shown a yield improvement for this enhanced integrated TFHM with regard to traditional TFHM
Keywords :
etching; integrated circuit interconnections; low-k dielectric thin films; masks; 65 nm; TFHM; enhanced trench first hard mask architecture; etch challenges; full vias; hard mask faceting; low-k backend integration; partial vias; yield improvement; Capacitance; Copper; Dielectric materials; Etching; Integrated circuit interconnections; Lithography; Plasma applications; Plasma materials processing; Plugs; Resists;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference, 2006 International
Conference_Location :
Burlingame, CA
Print_ISBN :
1-4244-0104-6
Type :
conf
DOI :
10.1109/IITC.2006.1648639
Filename :
1648639
Link To Document :
بازگشت