Title :
Combinatorial optimization models for the PLA folding problem
Author :
Macii, Enrico ; Wolf, Tarn
Author_Institution :
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
This paper considers combinatorial optimization models for the problem of reducing the chip area of programmable logic arrays (PLA´s) by folding. In particular, we focus on the variable and block folding problems, and we present theoretical optimization models based on the compatibility graph, on the incompatibility graph and on the representative hyper-graph of a PLA
Keywords :
circuit layout; graph theory; logic arrays; logic design; optimisation; PLA folding problem; block folding problem; chip area reduction; combinatorial optimization models; compatibility graph; incompatibility graph; programmable logic arrays; representative hyper-graph; variable folding problem; Automatic logic units; Boolean functions; Costs; Design optimization; Logic arrays; Logic circuits; Logic design; Programmable logic arrays; Simulated annealing; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 1993. Canadian Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-2416-1
DOI :
10.1109/CCECE.1993.332365
