A New Global Interconnect Paradigm: MIM Power-Ground Plane Capacitors

Author

Sekar, Deepak C. ; Demaray, Ernest ; Zhang, Hongmei ; Kohl, Paul A. ; Meindl, James D.

Author_Institution

Georgia Inst. of Technol., Atlanta, GA

fYear

2006

fDate

5-7 June 2006

Firstpage

48

Lastpage

50

Abstract

Based on scaling trends observed with a model for global interconnect pitch, a new paradigm is introduced for ASICs in which power and ground planes separated by a high k dielectric are placed on-chip. This gives a 4times reduction in on-chip IR drop, reduces di/dt noise due to package inductance by 2.6times without using any transistor area for decoupling capacitors (decaps), improves clock wire latency by 5%, reduces delay of global signal wires by 23% and decreases energy per bit for global signal wires by 22%. Thus, global interconnect problems could be substantially alleviated

Keywords

MIM devices; application specific integrated circuits; high-k dielectric thin films; integrated circuit interconnections; integrated circuit packaging; thin film capacitors; ASIC; MIM power-ground plane capacitors; clock wire latency improvement; decoupling capacitors; global interconnect paradigm; global signal delay reduction; high k dielectrics; Application specific integrated circuits; Capacitance; Clocks; Delay; MIM capacitors; Multiprocessor interconnection networks; Packaging; Power grids; Wire; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2006 International

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-0104-6

Type

conf

DOI

10.1109/IITC.2006.1648643

Filename

1648643