Low-loss LSI Interconnects on Novel "Partially Low-k Plugged Si Substrate" (PLP-Sub) for RF/ubiquitous Applications

A new "partially low-k plugged, silicon substrate" (PLP-sub) is proposed for the scaled-down system on chips (SoCs), especially for ubiquitous chips with the limited interconnect resources. By introducing partial dielectric surface region of the substrate, PLP-sub suppresses the parasitic capacitances between the interconnect-metal and the Si-substrate and increases the substrate resistance effectively, improving the interconnect performances including on-chip inductors. A two-layers stacked-inductor on the PLP-sub achieves 44% area-reduction along with suppressing the equivalent parasitic capacitance and substrate loss. The PLP-sub is effective for RF/ubiquitous applications with the limited interconnect resources