Multiple transient effects in SOI transistors: Systematic measurements and simulation

The use of partially depleted SOI CMOS technology in mainstream ULSI can be limited by transient floating body effects, that make circuit design problematic. Time-dependent V_T is observed in circuits, leading to unusual behaviours, such as current overshoot and undershoot. In order to properly evaluate the time-dependent floating-body effects on circuit performance, it is necessary to use a model (including both carrier generation and recombination) which predicts the transient responses of single devices to various front and back gate pulses. We present an enhanced version of SOISPICE-4.4 which provides the capabilities needed to correctly simulate floating-body transient effects in partially depleted circuits. The simulations are validated through systematic measurements over a wide range of experimental conditions: carrier generation and recombination-based transients, single and dual gate, back and front gate, various gate geometries. Most experiments were conducted at low V_D (to avoid impact-ionization and self-heating, i.e., to facilitate accurate calibration of the simulator) on partially depleted NMOS transistors fabricated on UNIBOND and Low-Dose SIMOX wafers. Four families of transients have been recorded, analyzed and simulated