A reusable embedded DRAM macrocell

Author

Diodato, P.W. ; Clemens, J.T. ; Troutman, W.W. ; Lindenberger, W.S.

Author_Institution

Bell Labs., Lucent Technol., Murray Hill, NJ, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

337

Lastpage

340

Abstract

A charged based analysis is used to compare three DRAM cells embedded in a 0.25 μm ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications

Keywords

DRAM chips; application specific integrated circuits; 0.25 micron; ASIC; bit-line response; charged based analysis; critical charge; hold time; multi-transistor cell; reusable embedded DRAM macrocell; sense amplifier sensitivity; wafer probe measurement; Application specific integrated circuits; Capacitors; Design methodology; Fabrication; Macrocell networks; Parasitic capacitance; Probes; Random access memory; Robustness; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606642

Filename

606642

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2171524