Title :
Systolic implementation of fractional decimators and interpolators
Author :
Abdel-Raheem, E. ; El-Guibaly, F. ; Antoniou, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Abstract :
New systolic implementations for decimators and interpolators with fractional compression/expansion factors are described. The new structures have the advantages of being modular, regular, hierarchical, and pipelined relative to known decimator/interpolator structures
Keywords :
digital arithmetic; digital filters; interpolation; pipeline processing; systolic arrays; decimators; fractional compression/expansion factors; hierarchical type; interpolators; modular structure; pipelined structure; systolic implementation; Finite impulse response filter; IIR filters; Image sampling; Interpolation; Nonlinear filters; Prototypes; Sampling methods; Signal processing; Signal sampling; Transfer functions;
Conference_Titel :
Electrical and Computer Engineering, 1993. Canadian Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-2416-1
DOI :
10.1109/CCECE.1993.332390
