A novel VLSI architecture of a multi membership function based MAX-MIN calculator circuit

The problem in widespread application of fuzzy logic in various fields can be attributed to the low processing speed of inference engine of a fuzzy processor. The inference engine demands high latency for calculating the matching degree (MD) between the fuzzified input and the antecedent membership functions (MF). In this work, the problem of MD calculation has been addressed by proposing and implementing, first time, a novel multi membership function (MMF) based MAX-MIN calculator circuit. The novelty of the proposed MAX-MIN calculator lies in handling the MMFs together in comparison to the exiting architectures of MAX-MIN circuits which deal with just one MF at a time. The proposed architecture calculates the matching degree between three types of MFs: Gaussian, Trapezoid and Triangular together. The proposed architecture has been modeled in VHDL and implemented in XILINX and Spartan field programmable gate arrays (FPGA). It has been observed that the proposed architecture, though handling multi membership functions, is power, area and speed efficient in comparison to existing architectures handling just one type of MF. The FPGA implementation of proposed MAX-MIN calculator has revealed that it uses 55.9% less 4-input look up tables, 60.9% less input-output buffers, 55.7% less number of occupied slices in comparison to the combined FPGA resources of the architectures based on Triangular, Trapezoid and Gaussian MFs used earlier.