DocumentCode :
2171814
Title :
Formal hardware verification by symbolic ternary trajectory evaluation
Author :
Bryant, Randal E. ; Seger, Carl-Johan H. ; Beatty, D.L.
Author_Institution :
Carnegie Mellon University
fYear :
1991
fDate :
21-21 June 1991
Firstpage :
397
Lastpage :
402
Keywords :
Analytical models; Automata; Circuit simulation; Computational modeling; Computer science; Formal verification; Hardware; Logic circuits; Multivalued logic; Pipeline processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1991. 28th ACM/IEEE
Conference_Location :
IEEE
Print_ISBN :
0-89791-395-7
Type :
conf
Filename :
979748
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2171814
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