Performance evaluation of different buffering schemes for balanced-gamma networks

Most of the existing multistage interconnection networks (MINs) used in packet switch architectures are delta networks based on 2×2 switching elements. To improve the performance of these networks, a number of schemes have been studied (like buffering, back-pressure, etc). To achieve an acceptable level of throughput these networks need a lot of buffers and/or a complex replication and dilation mechanism. The amount of required buffering can be reduced by increasing the performance of the basic structure. Because they are based on 4×4 switching elements, balanced gamma (BG) and kappa networks have better performance than banyan networks. Though the throughput of these networks is quite high, still it is not sufficient to meet the asynchronous transfer mode (ATM) requirements. To further improve the throughput of these networks, buffers should be provided. This paper analyses the performance of various buffering schemes on the balanced gamma networks