Design and implementation of single precision pipelined floating point co-processor

Author

Sangwan, Manisha ; Angeline, A. Anita

Author_Institution

VLSI Design SENSE, VIT Univ. Chennai, Chennai, India

fYear

2013

fDate

21-23 Sept. 2013

Firstpage

79

Lastpage

82

Abstract

Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency by 1.62 times. The logic is designed using Verilog HDL. Synthesis is done on Encounter by Cadence after timing and logic simulation.

Keywords

coprocessors; floating point arithmetic; hardware description languages; logic CAD; pipeline arithmetic; Encounter by Cadence; HDL; Verilog; arithmetic logic unit; arithmetic module; floating point ALU; floating point co-processor; floating point number; hardware description languages; logic design; logic simulation; pipelined architecture; single precision pipelining; Adders; Clocks; Computer architecture; Hardware design languages; Layout; Logic gates; Program processors; CLA; GDM; HDL; IEEE 754; clock-cycles; pipelining; verilog;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Electronic Systems (ICAES), 2013 International Conference on

Conference_Location

Pilani

Print_ISBN

978-1-4799-1439-5

Type

conf

DOI

10.1109/ICAES.2013.6659365

Filename

6659365