Title :
Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow
Author :
Mishra, Anadi ; Asati, Abhijit R. ; Raju, Kota Solomon
Author_Institution :
EEE Group, BITS - Pilani, Pilani, India
Abstract :
Partitioning and scheduling of dataflow graphs(DFGs) has been a matter of extensive research for ASIC based development. With the advent of partial reconfigurable hardware the need to schedule DFGs with restricted resources is required. In this research we test and extend the conventional scheduling algorithm suited for reconfiguration. In algorithm we restrict the flow as offered by Xilinx in PR design. The performance of such flow should be much significant than the conventional software execution flow. Hence we estimate the timing comparison of the software and the hardware flow.
Keywords :
data flow graphs; reconfigurable architectures; scheduling; ASIC based development; DFG scheduling; PR design; Xilinx PR flow; dataflow graph partitioning; dataflow graph scheduling; hardware flow timing; partial reconfigurable hardware; software execution flow; software flow timing; DFGs; Partial reconfiguration; Partitioning and Scheduling(PaSc); Xilinx;
Conference_Titel :
Advanced Electronic Systems (ICAES), 2013 International Conference on
Conference_Location :
Pilani
Print_ISBN :
978-1-4799-1439-5
DOI :
10.1109/ICAES.2013.6659371