A novel VLSI architecture of a defuzzifier unit for a fuzzy inference processor

The output of fuzzification process, a fuzzy data, is unsuitable for real time applications and needs to be converted into a crisp value. The process of defuzzification is very important and has a significant impact on the overall performance of a fuzzy inference system. In this work, a novel VLSI architecture of a defuzzifier is proposed, modeled in very high speed hardware description language (VHDL) and implemented in Vertex-4 field programmable gate array (FPGA). The proposed defuzzifier is based on the centre of gravity (COG) defuzzification method. Since weighted average method is generally being used because of its simplicity, however, it cannot be used for an asymmetrical output membership functions. Therefore, the VLSI architectural design of COG based defuzzifier is being done first time to our knowledge.