A high performance of deep-submicron gate ultra-thin film CMOS/SOI circuits with SIMOX substrate

Reduction of parasitic capacitances has predicted two-time high speed in deep-submicron CMOS/SIMOX ring oscillators (RO), where measurements are plotted for comparison with analytical models for an ultra-thin SOI film thickness of 30 (nm). Further, analytical lower bounds for power dissipations of CMOS/SOI inverters using a new gate capacitance model and conventional fixed gate capacitance are propounded. It is concluded that (1) the ROs have delay per stage of 55 ps at a gate height of 350 (nm), while the predicted highest speed per stage is 24 ps at the gate height reduced to zero for gate length of 0.1 μm and supply voltage of 2.5 v. (2) the power dissipations with 0.1- to 0.25-μm gate length are under 1.5 fJ in measurements, while the theoretical minima for power dissipations are no more than 0.2 fJ at supply voltage of 1.5 v. From these results, CMOS/SOI technology is promising for high speed and low power by reducing parasitic capacitance