Parameter extraction and modelling of short-channel LDD MOSFETs for VLSI applications

Author

Liang, J. ; Deen, M.J.

Author_Institution

Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada

fYear

1993

fDate

14-17 Sep 1993

Firstpage

821

Abstract

We report on the effects of temperature and biasing voltages on the parasitic resistance (R_p) and channel length reduction (ΔL) parameters in short-channel lightly-doped drain (LDD) NMOS transistors. These two parameters and their variation with operating conditions are required for the accurate modelling of MOS devices for VLSI applications. The results show that both R_p and ΔL vary with all operating bias voltages (drain, gate and substrate), and also with temperature. Using the extracted device parameters, current-voltage characteristics are simulated with SPICE and good agreement to experimental data is obtained. If the variations of these device parameters with operating conditions are not taken into account, the agreement is poor. Full details of the parameter extraction procedure and experimental results are described and discussed

Keywords

MOS integrated circuits; SPICE; VLSI; insulated gate field effect transistors; semiconductor device models; MOS devices; SPICE simulation; VLSI; biasing voltages; channel length; current-voltage characteristics; lightly-doped drain NMOS transistors; modelling; parameter extraction; parasitic resistance; short-channel LDD MOSFETs; temperature effects; Current-voltage characteristics; Data mining; MOS devices; MOSFETs; Parameter extraction; SPICE; Telecommunications; Temperature; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1993. Canadian Conference on

Conference_Location

Vancouver, BC

Print_ISBN

0-7803-2416-1

Type

conf

DOI

10.1109/CCECE.1993.332422

Filename

332422