Area optimized FPGA implementation of color edge detection

Author

Singh, Sushil ; Shekhar, C. ; Vohra, Anil

Author_Institution

Central Electron. Eng. Res. Inst. (CEERI), Pilani, India

fYear

2013

fDate

21-23 Sept. 2013

Firstpage

189

Lastpage

191

Abstract

A new area optimized VLSI architecture for color edge detection using Sobel operator is designed and implemented on Virtex-5 FPGA Platform. The proposed architecture uses only one processing element for computing gradients for all three R, G, and B color components and aims at reducing the FPGA resources usages. The FPGA resource usage is reduced more than 35% as compared to standard implementation which uses three gradient computation blocks. The system can robustly detect color edges at a frame rate of 50 frames per second (fps) for standard PAL (720×576) size video.

Keywords

VLSI; edge detection; field programmable gate arrays; image colour analysis; FPGA resources usages; RGB color components; Sobel operator; Virtex-5 FPGA platform; area optimized FPGA implementation; color edge detection; gradient computation blocks; optimized VLSI architecture; processing element; standard PAL size video; Computer architecture; Field programmable gate arrays; Image color analysis; Image edge detection; Real-time systems; Standards; Streaming media; Color Edge Detection; FPGA Implementation; VLSI Architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Electronic Systems (ICAES), 2013 International Conference on

Conference_Location

Pilani

Print_ISBN

978-1-4799-1439-5

Type

conf

DOI

10.1109/ICAES.2013.6659389

Filename

6659389