Author :
Arnal, V. ; Farcy, A. ; Aimadeddine, M. ; Icard, B. ; Guedj, C. ; Maitrejean, S. ; Todeschini, J. ; Besling, W. ; Brun, P. ; Ollier, E. ; Jacquemin, J.P. ; Delsol, R. ; Vannier, P. ; Mellier, M. ; Richard, E. ; Fox, R. ; Imbert, G. ; Lefriec, Y. ; Toffoli
Abstract :
A 45nm node BEOL integration scheme is presented with 140nm metal pitch at local and intermediate levels and 70nm via size. The dual damascene (DD) process is performed in a full porous low-k (k=2.5) at line and via level in order to meet RC performance requirements. Parametrical results show functional via chains and good line resistance and serpentine continuity at 45nm node dimensions. Copper resistivity and electromigration performances were investigated for line widths below 50 nm upon using ALD and PVD barriers
Keywords :
copper; electromigration; integrated circuit interconnections; low-k dielectric thin films; porous materials; silicon compounds; 45 nm; 70 nm; ALD barriers; BEOL integration; Cu; PVD barriers; SiOCH; copper resistivity; dual damascene process; electromigration performances; metal pitch; multi level interconnects; porous dielectric; serpentine continuity; via chains; Atherosclerosis; CMOS technology; Capacitance; Conductivity; Copper; Delay; Dielectric materials; Electromigration; Inorganic materials; Wire;
